In digital integrated circuits for high throughput rates, the so-called pipelining principle is frequently employed in order to achieve the necessary processing speed. For this purpose, pipeline registers are inserted as buffers in the data path. These pipeline registers can be realized efficiently as dynamic holding elements (latches) distributed over the data path. A holding element of this type contains a clocked switch and a storage capacitance, the parasitic input capacitance of a respective downstream logic block being utilized as the storage capacitance. Suitable clock signals control the holding elements or the switches and hence the timing of the data flow in the data path. The holding elements operate according to the master/slave principle, the so-called master latches being activated for about half a clock period and the so-called slave latches being inhibited and, during the next half of a clock period, the slave latches being activated and the master latches being inhibited. When the latches are inhibited, the logic state at the input of the downstream logic block remains dynamically stored in the form of an electric charge on the parasitic input capacitance. The time for which this charge remains stored is restricted typically to about one millisecond on account of leakage currents. This is unimportant during normal operation, when the clock signals have a switching frequency of the order of magnitude of several megahertz.
If the clock signal is absent for some reason, for example if the generator in the system fails or starts only after a delay when the system is switched on, then either all the switches of the master latches or all the switches of the slave latches are inhibited and remain in this state. The logic state on this storage node is undefined, for example, at the latest after about 1 millisecond. These nodes are at a potential which is determined only by parasitic resistances and leakage currents. Given typical dimensioning of the transistors in the latches, the voltage at this node will be between 1 volt and 4 volts. Since the inputs of the downstream CMOS gates are not, in this case, at a defined CMOS level, of 5 and 0 volts, for example, it is possible for a parallel-path current to flow in these gates. Although the parallel-path current lies in the microampere range in a single CMOS gate, the number of undefined nodes can become very large in a circuit with a high degree of pipelining, with the result that the total current consumption may lie in the ampere range in the event of failure of the clock signal.